Current microcontrollers, including PIC microcontrollers, use a random access memory (RAM) paging scheme to address all the data memory. This scheme is extremely cumbersome in that it takes several instructions to ensure that the user is writing or reading the proper address in RAM. It also complicates the job of the C-compiler since the C-compiler must keep track of which page is currently selected in RAM. This presents even more problems when handling interrupts.
In classic microcontroller architecture, increasing the op-code field to handle larger addresses would solve the address paging problem. However, increasing the op-code field has the disadvantage of increasing the size of the microcontroller and thus increasing the overall cost of the microcontroller. Another way to alleviate the RAM paging problem is to map all special function and register dedicated memory space that is available in every bank or page. This wastes precious RAM space since every location that is mapped takes up one general purpose RAM location in every bank. If the micro has eight (8) pages, seven (7) locations of RAM are wasted.
Therefore, a need existed to provide an improved microcontroller architecture and paging scheme. The improved microcontroller architecture and paging scheme must allow for direct access to special function registers. The improved microcontroller architecture and paging scheme must allow direct access to special function registers without modifying the page select register of the current instruction being used by the microcontroller. The improved microcontroller architecture and paging scheme must further allow for direct access to special function registers without increasing the size of the microcontroller.